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TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
.EATURES:
* * * * * * * * * * * * * *
IDT7290820
2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s Per-channel variable or constant throughput delay Automatic identification of ST-BUS(R)/GCI interfaces Accept streams of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s Automatic frame offset delay measurement Per-stream frame delay offset programming Per-channel high impedance output control Per-channel Processor Mode Control interface compatible to Intel/Motorola CPUs Connection memory block programming IEEE-1149.1 (JTAG) Test Port Available in 84-pin Plastic Leaded Chip Carrier (PLCC), 100-pin Ball Grid Array (BGA), 100-pin Plastic Quad Flatpack
(PQFP) and 100-pin Thin Quad Flatpack (TQFP) Operating Temperature Range -40C to +85C 5V Power Supply
DESCRIPTION:
The IDT7290820 is a non-blocking digital switch that has a capacity of 2,048 x 2,048 channels at a serial bit rate of 8.192 Mb/s, 1,024 x 1,024 channels at 4.096 Mb/s and 512 x 512 channels at 2.048 Mb/s. Some of the main features are: programmable stream and channel control, Processor Mode, input offset delay and high-impedance output control. Per-stream input delay control is provided for managing large multi-chip switches that transport both voice channel and concatenated data channels. In addition, input streams can be individually calibrated for input frame offset.
.UNCTIONAL BLOCK DIAGRAM
VCC
GND RESET
TMS
TDI
TDO
TCK
TRST
IC
ODE
Test Port
RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 TX0 TX1 TX2 TX3 TX4 TX5 TX6 TX7 TX8 TX9 TX10 TX11 TX12 TX13 TX14 TX15
Loopback Receive Serial Data Streams
Data Memory
Output MUX
Transmit Serial Data Streams
Internal Registers
Connection Memory
Timing Unit
Microprocessor Interface
CLK
F0i
FE/ WFPS HCLK
AS/ IM DS/ RD ALE
CS R/W/ A0-A7 DTA D8-D15/ WR AD0-AD7
CCO
5713 drw01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
JULY 2001
1
DSC-5713/4
2001
Integrated Device Technology, Inc.
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
PIN CON.IGURATIONS
A
RX0
A1 BALL PAD CORNER
TX13 TX11 TX10 RX1 TX14 TX12 RX4 RX8 RX9 RX3 RX6 VCC
TX8 TX9
TX7 TX6 VCC GND
TX4 TX5 DNC VCC
TX3 TX2 TX1 DTA
TX0 ODE D15 D13 D10 AD7 AD6 AD2
CCO D14 D12 D11 D9 D8 AD5 AD3 AD0
B
RX2
C
RX5 TX15 VCC VCC GND GND GND VCC GND GND
D
RX7
E
RX10 GND GND VCC GND GND VCC CS VCC AD4 AD1
F
RX11 RX12 VCC
G
RX13 RX15 CLK GND GND VCC A4 A3
H
RX14
FE/ HCLK
TCK RESET VCC TRST IC A0 WFPS A1 A2
J K
FOI TMS
TDI TDO
A7 R/W/RW IM A5 A6
DS/RD AS/ALE
1
2
3
4
5
6
7
8
9
10
5713 drw02
BGA: 1mm pitch, 11mm x 11mm (BC100-1, order code: BC) TOP VIEW
TX15 TX14 TX13 TX12 TX11 TX10 GND GND GND ODE VCC
TX9
TX8
TX7
TX6
TX5
TX4
TX3
TX2
TX1
INDEX
RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 F0i FE/HCLK GND CLK VCC
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
TX0
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
CCO DTA D15 D14 D13 D12 D11 D10 D9 D8 GND VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 GND
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
R/W/RW CS TDO IC RESET WFPS TMS TCK TRST TDI A0 A1 A2 A3 A4 A5 A6 A7 AS/ALE DS/RD IM
5713 drw03
NOTES: PLCC: 0.05in. pitch, 1.15in. x 1.15in. (PL84-1, order code: J) 1. DNC - Do Not Connect TOP VIEW 2. IC - Internal Connection, tie to GROUND for normal operation.
2
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
PIN CON.IGURATIONS (Continued)
TX12 TX15 TX14 TX11 TX13 TX10 DNC DNC GND GND GND ODE DNC 52 VCC TX5 DNC 51 TX7 TX4 TX3 TX9 TX6 TX2 TX8 TX1 TX0
57
66
75
71
62
70
61
74
65
69
60
59
56
68
73
64
55
72
63
DNC DNC RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 F0i FE/HCLK GND CLK VCC DNC DNC
76 77 78 79 90 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
67
58
54
53
DNC DNC CCO DTA D15 D14 D13 D12 D11 D10 D9 D8 GND VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 GND DNC DNC
18
14
23
15
10
19
11
20
24
16
12
21
13
4
8
WFPS
TDO
A0
A1
A4
A5
17
22
3
7
A2
A6
R/W/RW CS
A3
A7
DS/RD
TCK
TRST
IM
DNC
TDI
DNC
DNC
INDEX
AS/ALE
RESET
DNC
5713 drw04
TMS
TQFP: 0.50mm pitch, 14mm x 14mm (PN100-1, order code: PF) TOP VIEW
TX13 TX12 TX15 TX11 TX14 TX10 TX9 GND GND GND CCO DNC DNC ODE DNC
53
IC
25
5
1
2
6
9
DNC
DNC
52
DNC
DNC
TX8 VCC
TX7
TX6
TX2
61
TX1
55
64
73
78
69
60
77
68
59
72
63
62
71
80
76
67
58
75
79
70
66
57
74
65
56
54
51
DNC
TX5
TX4
TX3
TX0
RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 FOi FE/HCLK GND CLK
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
DTA D15 D14 D13 D12 D11 D10 D9 D8 GND VCC AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 GND
23
24
10
28
11
20
25 26
29
21
22
12
13
17
14
15
18
A0
16
A4
DNC
TDI TDO
A5
19
9
27
3
4
8
CS AS/ALE IM
DNC
RESET WFPS
DNC
DNC
DNC
DNC
TRST IC
DS/RD
INDEX
R/W/WR
DNC
VCC
DNC
A1
A6
A2
TMS
TCK
A3
A7
30
5
1
2
6
7
5713 drw05
PQFP: 0.65mm pitch, 14mm x 20mm (PQ100-2, order code: PQF) TOP VIEW 3
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
SYMBOL
GND Vcc TX0-15(1) RX0-15(1) F0i(1)
NAME
Ground. Vcc TX Output 0 to 15 (Three-state Outputs) RX Input 0 to 15 Frame Pulse
I/O
DESCRIPTION
Ground Rail. +5.0 Volt Power Supply. Serial data output stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0-1 in the IMS register. Serial data input stream. These streams may have data rates of 2.048, 4.096 or 8.192 Mb/s, depending upon the value programmed at bits DR0-1 in the IMS register. When the WFPS pin is LOW, this input accepts and automatically identifies frame synchronization signals formatted according to ST-BUS(R) and GCI specifications. When the WFPS pin is HIGH, this pin accepts a negative frame pulse which conforms to WFPS formats. When the WFPS pin is LOW, this pin is the frame measurement input. When the WFPS pin is HIGH, the HCLK (4.096 MHz clock) is required for frame alignment in the wide frame pulse (WFP) mode. Serial clock for shifting data in/out on the serial streams (RX/TX 0-15). Depending upon the value programmed at bits DR0-1 in the IMS register, this input accepts a 4.096, 8.192 or 16.384 MHz clock. JTAG signal that controls the state transitions of the TAP controller. This pin is pulled HIGH by an internal pullup when not driven. JTAG serial test instructions and data are shifted in on this pin. This pin is pulled HIGH by an internal pull-up when not driven. JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high-impedance state when JTAG scan is not enabled. Provides the clock to the JTAG test logic. This pin is pulled high by an internal pull-up when not driven. Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-reset state. This pin is pulled by an internal pull-up when not driven. This pin should be pulsed LOW on power-up, or held LOW, to ensure that the IDT7290820 is in the normal functional mode. Connect to GND for normal operation. This pin must be LOW for the IDT7290820 to function normally and to comply with IEEE 1114 (JTAG) boundary scan requirements. This input (active LOW) puts the IDT7290820 in its reset state that clears the device internal counters, registers and brings TX0-15 and microport data outputs to a high-impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. In normal operation, the RESET pin must be held LOW for a minimum of 100ns to reset the device. When 1, enables the wide frame pulse (WFP) Frame Alignment interface. When 0, the device operates in ST-BUS(R)/GCI mode. When non-multiplexed CPU bus operation is selected, these lines provide the A0-A7 address lines to the internal memories. For Motorola multiplexed bus operation, this input is DS. This active HIGH DS input works in conjunction with CS to enable the read and write operations. For Motorola non-multiplexed CPU bus operation, this input is DS. This active LOW input works in conjunction with CS to enable the read and write operations. For Intel multiplexed bus operation, this input is RD. This active LOW input sets the data bus lines (AD0-7, D8-15) as outputs. In the cases of Motorola non-multiplexed and multiplexed bus operations, this input is R/W. This input controls the direction of the data bus lines (AD0-7, D8-15) during a microprocessor access. For Intel multiplexed bus operation, this input is WR. This active LOW input is used with RD to control the data bus (AD0-7) lines as inputs. Active LOW input used by a microprocessor to activate the microprocessor port of IDT7290820. This input is used if multiplexed bus operation is selected via the IM input pin. For Motorola non-multiplexed bus operation, connect this pin to ground. This pin is pulled low by an internal pull-down when not driven. When IM is HIGH, the microprocessor port is in the multiplexed mode. When IM is LOW, the microprocessor port is in non-multiplexed mode. This pin is pulled low by an internal pull-down when not driven. These pins are the eight least significant data bits of the microprocessor port. In multiplexed mode, these pins are also the input address bits of the microprocessor port.
O I I
FE/HCLK(1) Frame Evaluation/ HCLK Clock (1) CLK Clock TMS TDI TDO TCK(1) TRST Test Mode Select Test Serial Data In Test Serial Data Out Test Clock Test Reset
I I I I O I I
IC(1) RESET(1)
Internal Connection Device Reset (Schmitt Trigger Input)
I I
WFPS(1) A0-7(1) DS/RD(1)
Wide Frame Pulse Select Address 0-7 Data Strobe/Read
I I I
R/W / WR(1) Read/Write / Write
I
CS(1) AS/ALE(1) IM(1) AD0-7(1)
Chip Select Address Strobe or Latch Enable CPU Interface Mode
I I I
Address/Data Bus 0 to 7 I/O
NOTE: 1. These pins are 5V tolerant.
4
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION(CONTINUED):
SYMBOL
D8-15 DTA(1)
(1)
NAME
Data Bus 8-15 Data Transfer Acknowledgment Control Output Output Drive Enable
I/O
I/O O
DESCRIPTION
These pins are the eight most significant data bits of the microprocessor port. This active LOW output signal indicates that a data bus transfer is complete. When the bus cycle ends, this pin drives HIGH and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required to hold a HIGH level when the pin is in high-impedance. This is a 4.096, 8.192 or 16.384 Mb/s output containing 512, 1,024 or 2.048 bits per frame respectively. The level of each bit is determined by the CCO bit in the connection memory. See External Drive Control Section. This is the output enable control for the TX0 to TX15 serial outputs. When ODE input is LOW and the OSB bit of the IMS register is LOW, TX0-15 are in a high-impedance state. If this input is HIGH, the TX0-15 output drivers are enabled. However, each channel may still be put into a high-impedance state by using the per channel control bit in the connection memory.
CCO(1) ODE(1)
O I
NOTE: 1. These pins are 5V tolerant.
5
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
.UNCTIONAL DESCRIPTION
The IDT7290820 is capable of switching up to 2,048 x 2,048, 64 Kbit/s PCM or N x 64 Kbit/s channel data. The device maintains frame integrity in data applications and minimum throughput delay for voice applications on a per channel basis. The serial input streams of the IDT7290820 can have a bit rate of 2.048, 4.096 or 8.192 Mb/s and are arranged in 125s wide frames, which contain 32, 64 or 128 channels respectively. The data rates on input and output streams are identical. In Processor Mode, the microprocessor can access input and output timeslots on a per channel basis allowing for transfer of control and status information. The IDT7290820 automatically identifies the polarity of the frame synchronization input signal and configures the serial streams to either ST-BUS(R) or GCI formats. With the variety of different microprocessor interfaces, IDT7290820 has provided an Input Mode pin (IM) to help integrate the device into different microprocessor based environments: Non-multiplexed or Multiplexed. These interfaces provide compatibility with multiplexed and Motorola non-multiplexed buses. The device can also resolve different control signals eliminating the use of glue logic necessary to convert the signals (R/W/WR, DS/RD, AS/ALE). The frame offset calibration function allows users to measure the frame offset delay using a frame evaluation pin (FE). The input offset delay can be programmed for individual streams using internal frame input offset registers, see Table 11. The internal loopback allows the TX output data to be looped around to the RX inputs for diagnostic purposes. A functional Block Diagram of the IDT7290820 is shown in Figure 1. DATA AND CONNECTION MEMORY The received serial data is converted to parallel format by internal serialto-parallel converters and stored sequentially in the data memory. The 8KHz input frame pulse (F0i) is used to generate channel and frame boundaries of the input serial data. Depending on the interface mode select (IMS) register, the usable data memory may be as large as 2,048 bytes. Data to be output on the serial streams (TX0-15) may come from either the data memory or connection memory. For data output from data memory (connection mode), addresses in the connection memory are used. For data to be output from connection memory, the connection memory control bits must set the particular TX output in Processor Mode. One time-slot before the data is to be output, data from either connection memory or data memory is read internally. This allows enough time for memory access and parallel-to-serial conversion. CONNECTION AND PROCESSOR MODES In the Connection Mode, the addresses of the input source data for all output channels are stored in the connection memory. The connection memory is mapped in such a way that each location corresponds to an output channel on the output streams. For details on the use of the source address data (CAB and SAB bits), see Table 13 and Table 14. Once the source address bits are programmed by the microprocessor, the contents of the data memory at the selected address are transferred to the parallel-to-serial converters and then onto a TX output stream.
By having the each location in the connection memory specify an input channel, multiple outputs can specify the same input address. This can be a powerful tool used for broadcasting data. In Processor Mode, the microprocessor writes data to the connection memory. Each location in the connection memory corresponds to a particular output stream and channel number and is transferred directly to the parallel-toserial converter one time-slot before it is to be output. This data will be output on the TX streams in every frame until the data is changed by the microprocessor. As the IDT7290820 can be used in a wide variety of applications, the device also has memory locations to control the outputs based on operating mode. Specifically, the IDT7290820 provides five per-channel control bits for the following functions: processor or connection mode, constant or variable delay, enables/three-state the TX output drivers and enables/disable the loopback function. In addition, one of these bits allows the user to control the CCO output. If an output channel is set to a high-impedance state through the connection memory, the TX output will be in a high-impedance state for the duration of that channel. In addition to the per-channel control, all channels on the ST-BUS(R) outputs can be placed in a high impedance state by either pulling the ODE input pin low or programming the Output Stand-By (OSB) bit in the interface mode selection register. This action overrides the per-channel programming in the connection memory bits. The connection memory data can be accessed via the microprocessor interface. The addressing of the devices internal registers, data and connection memories is performed through the address input pins and the Memory Select (MS) bit of the control register. For details on device addressing, see Software Control and Control Register bits description (Table 4, 6 and 7). SERIAL DATA INTERFACE TIMING The master clock frequency must always be twice the data rate. For serial data rates of 2.048, 4.096 or 8.192 Mb/s, the master clock (CLK) must be either at 4.096, 8.192 or 16.384 MHz respectively. The input and output stream data rates will always be identical. The IDT7290820 provides two different interface timing modes ST-BUS(R)/ GCI and WFP (wide frame pulse). If the WFPS pin is high, the IDT7290820 is in the wide frame pulse (WFP) frame alignment mode. In ST-BUS(R)/GCI mode, the input 8 KHz frame pulse can be in either ST-BUS(R) or GCI format. The IDT7290820 automatically detects the presence of an input frame pulse and identifies it as either ST-BUS(R) or GCI. In ST-BUS(R) format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of CLK, three quarters of the way into the bit cell, see Figure 7. In GCI format, every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of CLK at three quarters of the way into the bit cell, see Figure 8. WIDE FRAME PULSE (WFP) FRAME ALIGNMENT TIMING When the device is in WFP frame alignment mode, the CLK input must be at 16.384 MHz, the FE/HCLK input is 4.096 MHz and the 8 KHz frame pulse is in ST-BUS(R) format. The timing relationship between CLK, HCLK and the frame pulse is shown in Figure 9. When WFPS pin is high, the frame alignment evaluation feature is disabled. However, the frame input offset registers may still be programmed to compensate for the varying frame delays on the serial input streams.
6
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
SWITCHING CON.IGURATIONS
The IDT7290820 can operate at different speeds. To configure the maximum non-blocking switching data rate, the two DR bits in the IMS register are used. Following are the possible configurations: 2.048 Mb/s Serial Links (DR0=0, DR1=0) When the 2.048 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 32, 64 Kbit/s channels each. This mode requires a CLK of 4.096 MHz and allows a maximum non-blocking capacity of 512 x 512 channels. 4.096 Mb/s Serial Links (DR0=1, DR1=0) When the 4.096 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 64, 64 Kbit/s channels each. This mode requires a CLK of 8.192 MHz and allows a maximum non-blocking capacity of 1,024 x 1,024 channels. 8.192 Mb/s Serial Links (DR0=0, DR1=1) When the 8.192 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 128, 64 Kbit/s channels each. This mode requires a CLK of 16.384 MHz and allows a maximum non-blocking capacity of 2,048 x 2,048 channels. Table 1 summarizes the switching configurations and the relationship between different serial data rates and the master clock frequencies. INPUT FRAME OFFSET SELECTION Input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. F0i). Although all input data comes in at the same speed, delays can be caused by variable path serial backplanes and variable path lengths which may be implemented in large centralized and distributed switching systems. Because data is often delayed, this feature is useful in compensating for the skew between clocks. Each input stream can have its own delay offset value by programming the frame input offset registers (FOR). The maximum allowable skew is +4.5 master clock (CLK) periods forward with resolution of 1/2 clock period. The output frame offset cannot be offset or adjusted. See Figure 5, Table 11 and 12 for delay offset programming. SERIAL INPUT FRAME ALIGNMENT EVALUATION The IDT7290820 provides the frame evaluation (FE) input to determine different data input delays with respect to the frame pulse F0i. A measurement cycle is started by setting the start frame evaluation (SFE) bit low for at least one frame. When the SFE bit in the IMS register is changed
from low to high, the evaluation starts. Two frames later, the complete frame evaluation (CFE) bit of the frame alignment register (FAR) changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 11 of the FAR register. The SFE bit must be set to zero before a new measurement cycle started. In ST-BUS(R) mode, the falling edge of the frame measurement signal (FE) is evaluated against the falling edge of the ST-BUS(R) frame pulse. In GCI mode, the rising edge of FE is evaluated against the rising edge of the GCI frame pulse. See Table 10 & Figure 4 for the description of the frame alignment register. This feature is not available when the WFP Frame Alignment mode is enabled (i.e., when the WFPS pin is connected to VCC). MEMORY BLOCK PROGRAMMING The IDT7290820 provides users with the capability of initializing the entire connection memory block in two frames. To set bits 11 to 15 of every connection memory location, first program the desired pattern in bits 5 to 9 of the IMS register. The block programming mode is enabled by setting the memory block program (MBP) bit of the control register high. When the block programming enable (BPE) bit of the IMS register is set to high, the block programming data will be loaded into the bits 11 to 15 of every connection memory location. The other connection memory bits (bit 0 to bit 10) are loaded with zeros. When the memory block programming is complete, the device resets the BPE bit to zero. LOOPBACK CONTROL The loopback control (LPBK) bit of each connection memory location allows the TX output data to be looped backed internally to the RX input for diagnostic purposes. If the LPBK bit is high, the associated TX output channel data is internally looped back to the RX input channel (i.e., data from TX n channel m routes to the RX n channel m internally); if the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of frame delay offset registers must be set to zero.
DELAY THROUGH THE IDT7290820
The switching of information from the input serial streams to the output serial streams results in a throughput delay. The device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on the per-channel basis. For voice applications, variable throughput delay is best as it ensures minimum delay between input and output data. In wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. The delay through the device varies according to the type of throughput delay selected in the V/C bit of the connection memory. VARIABLE DELAY MODE (V/C BIT = 0) In this mode, the delay is dependent only on the combination of source and destination channels and is independent of input and output streams. The minimum delay achievable in the IDT7290820 is three time-slots. If the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame (channel n, frame p+1). The same is true if input channel n is switched to output channel n+1 or n+2. If the input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same frame. Table 2 shows the possible delays for the IDT7290820 in the variable delay mode.
TABLE 1 SWITCHING CON.IGURATION
Serial Interface Data Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Master Clock Required (MHz) 4.096 8.192 16.384 Matrix Channel Capacity 512 x 512 1,024 x 1,024 2,048 x 2,048
7
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
CONSTANT DELAY MODE (V/C BIT = 1) In this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. Input channel data is written into the data memory buffers during frame n will be read out during frame n+2. In the IDT7290820, the minimum throughput delay achievable in the constant delay mode will be one frame. For example, in 2.048 Mb/s mode, when input time-slot 31 is switched to output time-slot 0. The maximum delay of 94 time-slots of delay occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame. See Table 3.
MICROPROCESSOR INTER.ACE
The IDT7290820 provides a parallel microprocessor interface for multiplexed or non-multiplexed bus structures. This interface is compatible with Motorola non-multiplexed and multiplexed buses. If the IM pin is low a Motorola non-multiplexed bus should be connected to the device. If the IM pin is high, the device monitors the AS/ALE and DS/RD to determine what mode the IDT7290820 should operate in. If DS/RD is low at the rising edge of AS/ALE, then the mode 1 multiplexed timing is selected. If DS/RD is high at the rising edge of AS/ALE, then the mode 2 multiplexed bus timing is selected. For multiplexed operation, the required signals are the 8-bit data and address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/Address latch enable (AS/ ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR), Chip select (CS) and Data transfer acknowledge (DTA). See Figure 12 and Figure 13 for multiplexed parallel microport timing. For the Motorola non-multiplexed bus, the required signals are the 16-bit data bus (AD0-AD7, D8-D15), 8-bit address bus (A0-A7) and 4 control lines (CS, DS, R/W and DTA). See Figure 14 and 15 for Motorola non-multiplexed microport timing. The IDT7290820 microport provides access to the internal registers, connection and data memories. All locations provide read/write access except for the data memory and the frame alignment register which are read only. MEMORY MAPPING The address bus on the microprocessor interface selects the internal registers and memories of the IDT7290820. If the A7 address input is low, then A6 through A0 are used to address the interface mode selection (IMS), control (CR), frame alignment (FAR) and frame input offset (FOR) registers (Table 4). If the A7 is high, then A6 through A0 are used to select 32, 64, or 128 locations corresponding to data rate of the ST-BUS(R). The address input lines and the stream address bits (STA) of the control register allow access to the entire data and connection memories. The control and IMS registers together control all the major functions of the device, see Figure 3. As explained in the Serial Data Interface Timing and Switching Configurations sections, after system power-up, the IMS register should be programmed immediately to establish the desired switching configuration. The data in the control register consists of the memory block programming bit (MBP), the memory select bit (MS) and the stream address bits (STA). As explained in the Memory Block Programming section, the MBP bit allows the
entire connection memory block to be programmed. The memory select bit is used to designate the connection memory or the data Memory. The stream address bits select internal memory subsections corresponding to input or output serial streams. The data in the IMS register consists of block programming bits (BPD0BPD4), block programming enable bit (BPE), output stand by bit (OSB), start frame evaluation bit (SFE) and data rate selection bits (DR0-1). The block programming and the block programming enable bits allows users to program the entire connection memory (see Memory Block Programming section). If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all ST-BUS(R) output drivers. If the ODE pin is high, the contents of the OSB bit is ignored and all TX output drivers are enabled. CONNECTION MEMORY CONTROL The CCO pin is a 4.096, 8.192 or 16.384 Mb/s output, which carries 512, 1,024 or 2,048 bits, respectively. The contents of the CCO bit of each connection memory location are output on the CCO pin once every frame. The contents of the CCO bits of the connection memory are transmitted sequentially on to the CCO pin and are synchronous with the data rates on the other serial streams. The CCO bit is output one channel before the corresponding channel on the serial streams. For example, in 2.048 Mb/s mode (32 channels per frame), the contents of the CCO bit in position 0 (TX0, CH0) of the connection memory is output on the first clock cycle of channel 31 through CCO pin. The contents of the CCO bit in position 32 (TX1, CH0) of the connection memory is output on the second clock cycle of channel 31 via CCO pin. If the ODE pin or the OSB bit is high, the OE bit of each connection memory location controls the output drivers-enables (if high) or disables (if low). See Table 5 for detail. The processor channel (PC) bit of the connection memory selects between Processor Mode and Connection Mode. If high, the contents of the connection memory are output on the TX streams. If low, the stream address bit (SAB) and the channel address bit (CAB) of the connection memory defines the source information (stream and channel) of the time-slot that will be switched to the output from data memory. The V/C (Variable/Constant Delay) bit in each connection memory location allows the per-channel selection between variable and constant throughput delay modes. If the LPBK bit is high, the associated TX output channel data is internally looped back to the RX input channel (i.e., RX n channel m data comes from the TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For proper per-channel loopback operation, the contents of the frame delay offset registers must be set to zero.
INITIALIZATION O. THE IDT7290820
After power up, the state of the connection memory is unknown. As such, the outputs should be put in high impedance by holding the ODE low. While the ODE is low, the microprocessor can initialize the device, program the active paths, and disable unused outputs by programming the OE bit in connection memory. Once the device is configured, the ODE pin (or OSB bit depending on initialization) can be switched.
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IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
Control Register CRb7 CRb6 CRb5 CRb4
COMMERCIAL TEMPERATURE RANGE
CRb3 CRb2 CRb1 CRb0
CRb4
1 0 The Control Register is only accessed when A7-A0 are all zeroed. When A7 =1, up to 128 bytes are randomly accessable via A0-A6 at any one instant. Of which stream these bytes (channels) are accessed is determined by the state of CRb3 -CRb0.
Connection Memory
Data Memory
Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 0 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 1 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 2 Channel 127 Channel 127 Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel Channel 127 127 127 127 127 127 127 127 127 127 127 127 127 127
CRb3 CRb2 CRb1 CRb0 Stream 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
10000000
10000001
10000010
11111111
External Address Bits
A7-A0
5713 drw06
Figure 3. Addressing Internal Memories
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IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
TABLE 2 VARIABLE THROUGHPUT DELAY VALUE
Input Rate m2.048 Mb/s 4.096 Mb/s 8.192 Mb/s
m > n+2 m-n time-slots m-n time slots m-n time-slots
TABLE 3 CONSTANT THROUGHPUT DELAY VALUE
Input Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Delay for Constant Throughput Delay Mode (m - output channel number) (n - input channel number) 32 + (32 - n) + m time-slots 64 + (64 - n) + m time-slots 128 + (128 - n) + m time-slots
TABLE 4 INTERNAL REGISTER AND ADDRESS MEMORY MAPPING
A7(1) A6 A5 A4 A3 A2 A1 A0 Location 0 0 0 0 0 0 0 0 Control Register, CR 0 0 0 0 0 0 0 1 Interface Mode Selection Register, IMS 0 0 0 0 0 0 1 0 Frame Alignment Register, FAR 0 0 0 0 0 0 1 1 Frame Input Offset Register 0, FOR0 0 0 0 0 0 1 0 0 Frame Input Offset Register 1, FOR1 0 0 0 0 0 1 0 1 Frame Input Offset Register 2, FOR2 0 0 0 0 0 1 1 0 Frame Input Offset Register 3, FOR3 1 0 0 0 0 0 0 0 Ch0 1 0 0 0 0 0 0 1 Ch1 1 0 0 . . . . . . 1 0 0 1 1 1 1 0 Ch30 1 0 0 1 1 1 1 1 Ch31 1 0 1 0 0 0 0 0 Ch32 1 0 1 0 0 0 0 1 Ch33 1 0 1 . . . . . . 1 0 1 1 1 1 1 0 Ch62 1 0 1 1 1 1 1 1 Ch63 1 1 0 0 0 0 0 0 Ch64 1 1 0 0 0 0 0 1 Ch65 1 1 0 . . . . . . 1 1 1 1 1 1 1 0 Ch126 1 1 1 1 1 1 1 1 Ch127 Notes: 1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers. 2. Channels 0 to 31 are used when serial interface is at 2.048 Mb/s mode 3. Channels 0 to 63 are used when serial interface is at 4.096 Mb/s mode. 4. Channels 0 to 127 are used when serial interface is at 8.192 Mb/s mode.
(Note 2)
(Note 3)
(Note 4)
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IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
TABLE 5 OUTPUT HIGH IMPEDANCE CONTROL
OE bit in Connection Memory 0 1 1 1 1 ODE pin Don't Care 0 0 1 1 OSB bit in IMS Register Don't Care 0 1 1 0 TX Output Driver Status Per Channel High-Impedance High-Impedance Enable Enable Enable
TABLE 6 CONTROL REGISTER (CR) BITS
Read/Write Address: Reset Value: 15 0 Bit 15-6 5 4 14 0 13 0 00H, 0000H. 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 MBP 4 MS 3 2 1 0
STA3 STA2 STA1 STA0
Name Unused MBP (Memory Block Program) MS (Memory Select) STA3-0 (Stream Address Bits)
Description Must be zero for normal operation. When 1, the connection memory block programming feature is ready for the programming of Connection Memory high bits, bit 11 to bit 15. When 0, this feature is disabled. When 0, connection memory is selected for read or write operations. When 1, the data memory is selected for read operations and connection memory is selected for write operations. (No microprocessor write operation is allowed for the data memory). The binary value expressed by these bits refers to the input or output data stream, which corresponds to the subsection of memory made accessible for subsequent operations. (STA3 = MSB, STA0 = LSB)
3-0
TABLE 7 VALID ADDRESS LINES .OR DI..ERENT BIT RATES
Input/Output Data Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Valid Address Lines A4, A3, A2, A1, A0 A5, A4, A3, A2, A1, A0 A6, A5, A4, A3, A2, A1, A0
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IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
TABLE 8 INTER.ACE MODE SELECTION (IMS) REGISTER BITS
Read/Write Address: Reset Value: 15 0 14 0 13 0 01H, 0000H. 12 0 11 0 10 0 9 8 7 6 5 4 BPE 3 OSB 2 SFE 1 DR1 0 DR0
BPD4 BPD3 BPD2 BPD1 BPD0
Bit 15-10 9-5 Unused
Name Must be zero for normal operation. BPD4-0 (Block Programming Data)
Description These bits carry the value to be loaded into the connection memory block whenever the memory block programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD4-0 are loaded into bit 15 and 11 of the connection memory. Bit 10 to bit 0 of the connection memory are set to 0. A zero to one transition of this bit enables the memory block programming function. The BPE and BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set HIGH, the device requires two frames to complete the block programming. After the programming function has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to ensure proper operation. When BPE = 1, the other bit in the IMS register must not be changed for two frames to ensure proper operation. When ODE = 0 and OSB = 0, the output drivers of TX0 to TX15 are in high impedance mode. When ODE= 0 and OSB = 1, the output driver of TX0 to TX15 function normally. When ODE = 1, TX0 to TX15 output drivers function normally. A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from zero to one, the evaluation procedure stops. To start another fame evaluation cycle, set this bit to zero for at least one frame. Input/Output data rate selection. See Table 9 for detailed programming.
4
BPE (Begin Block Programming Enable)
3
OSB (Output Stand By) SFE (Start Frame Evaluation) DR0-1 (Data Rate Select)
2
1-0
TABLE 9 SERIAL DATA RATE SELECTION (16 INPUT x 16 OUTPUT)
DR1 0 0 1 1 DR0 0 1 0 1 Data Rate Selected 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s Reserved Master Clock Required 4.096 MHz 8.192 MHz 16.384 MHz Reserved
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IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
TABLE 10 .RAME ALIGNMENT REGISTER (.AR) BITS
Read/Write Address: Reset Value: 15 0 Bit 15-13 12 11 10-0 14 0 13 0 Name Unused CFE (Complete Frame Evaluation) FD11 (Frame Delay Bit 11) FD10-0 (Frame Delay Bits) 02H, 0000H. 12 CFE 11 10 9 FD9 8 FD8 7 FD7 6 FD6 5 FD5 4 FD4 3 FD3 2 FD2 1 FD1 0 FD0
FD11 FD10
Description Must be zero for normal operation. When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0. The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to 1/2 CLK cycle. The binary value expressed in these bits refers to the measured input offset value. These bits are rest to zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 - MSB, FD0 - LSB)
ST-BUS Frame
CLK
Offset Value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FE Input
(FD[10:0] = 06H) (FD11 = 0, sample at CLK LOW phase)
GCI Frame
CLK
Offset Value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FE Input
(FD[10:0] = 09H) (FD11 = 1, sample at CLK HIGH phase)
5713 drw07
Figure 4. Example for Frame Alignment Measurement 13
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
TABLE 11 .RAME INPUT O..SET REGISTER (.OR) BITS
Read/Write Address: 03H for FOR0 register, 04H for FOR1 register, 05H for FOR2 register, 06H for FOR3 register, 0000H for all FOR registers. 12
DLE3
Reset Value: 15
OF32
14
OF31
13
OF30
11
OF22
10
OF21
9
OF20
8
DLE2
7
OF12
6
OF11
5
OF10
4
DLE1
3
OF02
2
OF01
1
OF00
0
DLE0
15
OF72
14
OF71
13
OF70
12
DLE7
11
OF62
10
OF61
9
OF60
8
FOR0 Register 7 6
OF52 OF51
5
OF50
4
DLE5
3
OF42
2
OF41
1
OF40
0
DLE4
DLE6
15
14
13
12
11
10
9
8
FOR1 Register 7 6
OF92 OF91
5
OF90
4
DLE9
3
OF82
2
OF81
1
OF80
0
DLE8
OF112 OF111 OF110 DLE11 OF102 OF101 OF100 DLE10
15
14
13
12
11
10
9
8
FOR2 Register 7 6
5
4
3
2
1
0
OF152 OF151 OF150 DLE15 OF142 OF141 OF140 DLE14 OF132 OF131 OF130 DLE13 OF122 OF121 OF120 DLE12
FOR3 Register Name OFn2, OFn1, OFn0 (Offset Bits 2, 1 & 0) DLEn (Data Latch Edge)
(1)
Description These three bits define how long the serial interface receiver takes to recognize and store bit 0 from the RX input pin: i.e., to start a new frame. The input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse input signal is applied to the F0i input of the device. See Figure 5. ST-BUS(R) mode: GCI mode: DLEn = 0, if clock rising edge is at the 3/4 point of the bit cell. DLEn = 1, if when clock falling edge is at the 3/4 of the bit cell. DLEn = 0, if clock falling edge is at the 3/4 point of the bit cell. DLEn = 1, if when clock rising edge is at the 3/4 of the bit cell.
NOTE: 1. n denotes an input stream number from 0 to 15.
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IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
TABLE 12 O..SET BITS (O.n2, O.n1, O.n0, DLEn) & .RAME DELAY BITS (.D11, .D2-0)
Input Stream Offset No clock period shift (Default) + 0.5 clock period shift + 1.0 clock period shift + 1.5 clock period shift + 2.0 clock period shift + 2.5 clock period shift + 3.0 clock period shift + 3.5 clock period shift + 4.0 clock period shift + 4.5 clock period shift FD11 1 0 1 0 1 0 1 0 1 0 Measurement Result from Frame Delay Bits FD2 0 0 0 0 0 0 0 0 1 1 FD1 0 0 0 0 1 1 1 1 0 0 FD0 0 0 1 1 0 0 1 1 0 0 OFn2 0 0 0 0 0 0 0 0 1 1 Corresponding Offset Bits OFn1 0 0 0 0 1 1 1 1 0 0 OFn0 0 0 1 1 0 0 1 1 0 0 DLEn 0 1 0 1 0 1 0 1 0 1
ST-BUS F0i
CLK
RX Stream
Bit 7
offset = 0,
DLE = 0
RX Stream
Bit 7
offset = 1,
DLE = 0
RX Stream
Bit 7
offset = 0,
DLE = 1
RX Stream
Bit 7
offset = 1, DLE = 1
denotes the 3/4 point of the bit cell
GCI F0i
CLK
RX Stream
Bit 0
offset = 0,
DLE = 0
RX Stream
Bit 0
offset = 1,
DLE = 0
RX Stream
Bit 0
offset = 0,
DLE = 1
RX Stream
Bit 0
offset = 1, DLE = 1
denotes the 3/4 point of the bit cell
5713 drw08
Figure 5. Examples for Input Offset Delay Timing 15
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
TABLE 13 CONNECTION MEMORY BITS
15
LPBK
14
V/C
13
PC
12
CCO
11
OE
10
SAB3
9
SAB2
8
SAB1
7
SAB0
6
CAB6
5
CAB5
4
CAB4
3
CAB3
2
CAB2
1
CAB1
0
CAB0
Bit 15 14
13
Name LPBK (Per Channel Loopback) V/C (Variable/Constant Throughput Delay) PC (Processor Channel) CCO (Control Channel Output) OE (Output Enable) SAB3-0 (Source Stream Address Bits) CAB6-0 (Source Channel Address Bits)
Description When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback operations, set the delay offset register bits OFn[2:0] to zero for the streams which are in the loopback mode. This bit is used to select between the variable (LOW) and constant delay (HIGH) mode on a per-channel basis. When 1, the contents of the connection memory are output on the corresponding output channel and stream. Only the lower byte (bit 7 - bit 0) will be output to the TX output pins. When 0, the contents of the connection memory are the data memory address of the switched input channel and stream. This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first. This bit enables the TX output drivers on a per-channel basis. When 1, the output driver functions normally. When 0, the output driver is in a high-impedance state. The binary value is the number of the data stream for the source of the connection. The binary value is the number of the channel for the source of the connection.
12 11 10-8,7(1) 6-0(1)
NOTE: 1. If bit 13 (PC) of the corresponding connection memory location is 1 (device in processor mode), then these entire 8 bits (SAB0, CAB6 - CAB0) are output on the output channel and stream associated with this location.
TABLE 14 CAB BIT PROGRAMMING .OR DI..ERENT DATA RATES
Data Rate 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s CAB Bits Used to Determine the Source Channel of the Connection CAB4 to CAB0 (32 channel/input stream) CAB5 to CAB0 (64 channel/input stream) CAB6 to CAB0 (128 channel/input stream)
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IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
JTAG SUPPORT
The IDT7290820 JTAG interface conforms to the Boundary-Scan standard IEEE-1149.1. This standard specifies a design-for-testability technique called Boundary-Scan Test (BST). The operation of the boundary-scan circuitry is controlled by an external test access port (TAP) Controller. TEST ACCESS PORT (TAP) The Test Access Port (TAP) provides access to the test functions of the IDT7290820. It consists of three input pins and one output pin. *Test Clock Input (TCK) TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remain independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. *Test Mode Select Input (TMS) The logic signals received at the TMS input are interpreted by the TAP Controller to control the test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to Vcc when it is not driven from an external source. *Test Data Input (TDI) Serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the TMS input. Both registers are described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses. This pin is internally pulled to Vcc when it is not driven from an external source. *Test Data Output (TDO) Depending on the sequence previously applied to the TMS input, the contents of either the instruction register or data register are serially shifted out towards the TDO. The data out of the TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan cells, the TDO driver is set to a high impedance state. *Test Reset (TRST) Reset the JTAG scan structure. This pin is internally pulled to VCC.
INSTRUCTION REGISTER In accordance with the IEEE 1149.1 standard, the IDT7290820 uses public instructions. The IDT7290820 JTAG Interface contains a two-bit instruction register. Instructions are serially loaded into the instruction register from the TDI when the TAP Controller is in its shifted-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between TDI and TDO during data register scanning. See Table below for instruction decoding.
Value 11 10 01 00
Instruction Bypass Sample/Period Sample/Period EXTEST
Function Select ByPass Register Select Boundry Scan Register Select Boundry Scan Register Select Boundry Scan Register
JTAG Instruction Register Decoding TEST DATA REGISTER As specified in IEEE 1149.1, the IDT7290820 JTAG Interface contains two test data registers: *The Boundary-Scan register The Boundary-Scan register consists of a series of Boundary-Scan cells arranged to form a scan path around the boundary of the IDT7290820 core logic. *The Bypass Register The Bypass register is a single stage shift register that provides a one-bit path from TDI to its TDO. The IDT7290820 boundary scan register contains 118 bits. Bit 0 in Table 15 Boundary Scan Register is the first bit clocked out. All three-state enable bits are active high.
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IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
TABLE 15 BOUNDARY SCAN REGISTER BITS
Device Pin TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 ODE CCO DTA D15 D14 D13 D12 D11 D10 D9 D8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 IM AD/ALE CS R/W / WR DS/RD A7 A6 A5 Boundary Scan Bit 0 to bit 117 Three-State Output Input Control Scan Cell Scan Cell 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Device Pin A4 A3 A2 A1 A0 WFPS RESET CLK FE/HCLK F0i RX15 RX14 RX13 RX12 RX11 RX10 RX9 RX8 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 TX15 TX14 TX13 TX12 TX11 TX10 TX9 TX8 Boundary Scan Bit 0 to bit 117 Three-State Output Input Control Scan Cell Scan Cell 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117
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IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC Vi IO TS PD Parameter Supply Voltage Voltage on Digital Inputs Current at Digital Outputs Storage Temperature Package Power Dissapation -65 GND -0.3 Min. Max. 6.0 VCC +0.3 20 +125 2 Unit V V mA C W
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC VIH VIL TOP Parameter Positive Supply Input HIGH Voltage Input LOW Voltage Operating Temperature Commercial Min. 4.75 2.4 GND -40 Typ. Max. 5.25 VCC 0.4 +85 Units V V V C
NOTE: 1. Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
NOTE: 1. Voltages are with respect to ground unless other wise stated.
DC ELECTRICAL CHARACTERISTICS
Symbol ICC(1) Characteristics Supply Current @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s Min. 2.0 2.4 Typ. 16 26 50 Max. 25 40 75 0.8 15 50 10 5 0.4 10 Units mA mA mA V V A A pF A V V pF
VIH VOL IIL(2) IBL CI IOZ VOH VOL CO
Input HIGH Voltage Input LOW Voltage Input Leakage (input pins) Input Leakage (I/O pins) Input Pin Capacitance High-impedance Leakage Output HIGH Voltage Output LOW Voltage Output Pin Capacitance
NOTE: 1. Outputs Unloaded. 2. For TDI, TMS, TCK, TRST, AS/ALE and IM pins, the maximum leakage current is 50A.
Test Point
VCC
S1 is open circuit except when testing output levels or high impedance states. S2 is switched to VCC or GND when testing output levels or high impedance states.
Output Pin S1 CL GND
RL S2 GND
5713 drw09
Figure 6. Output Load 19
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - .RAME PULSE AND CLK
Symbol tFPW Characteristics Frame Pulse Width (ST-BUS , GCI)
(R)
Min. Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s 26 26 26 10 16 190 110 55 85 50 20 85 50 20 Bit rate = 8.192 Mb/s 195 10 20 Bit rate = 8.192 Mb/s Bit rate = 8.192 Mb/s Bit rate = 8.192 Mb/s 190 85 85 -10
Typ.
Max. 295 145 80 300 150 70 150 75 40 150 75 40 10 295 150 150 300 150 150 10 10
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tFPS tFPH tCP
Frame Pulse Setup time before CLK falling (ST-BUS(R) or GCI) Frame Pulse Hold Time from CLK falling (ST-BUS(R) or GCI) CLK Period Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s
tCH
CLK Pulse Width HIGH
tCL
CLK Pulse Width LOW
tr, tf tHFPW tHFPS tHFPH tHCP tHCH tHCL tHr, tHf tDIF
Clock Rise/Fall Time Wide Frame Pulse Width Frame Pulse Setup Time before HCLK falling Frame Pulse Hold Time from HCLK falling HCLK (4.096 MHz) Period HCLK (4.096 MHz) Pulse Width HIGH HCLK (4.096 MHz) Pulse Width LOW HCLK Rise/Fall Time Delay between falling edge of HCLK and falling edge of CLK
AC ELECTRICAL CHARACTERISTICS - SERIAL STREAMS (1)
Symbol tSIS tSIH tSOD tDZ tZD tODE tXCD Characteristics RX Setup Time RX Hold Time TX Delay - Active to Active TX Delay - Active to High-Z TX Delay - High-Z to Active Output Driver Enable (ODE) Delay CCO Output Delay Min. 0 20 Typ. Max. 39 58 37 37 37 48 58 Unit ns ns ns ns ns ns ns ns ns CL = 30pF CL = 200pF RL = 1K, CL = 200pF RL = 1K, CL = 200pF RL = 1K, CL = 200pF CL = 30pF CL = 200pF Test Conditions
NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
20
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
tFPW
F0i
tFPS
CLK
tFPH
tCP
tCH
tCL
tr
tf
tSOD
TX Bit 0, Last Ch (1) Bit 7, Channel 0 Bit 6, Channel 0 Bit 5, Channel 0
tSIS
RX Bit 0, Last Ch(1)
tSIH
Bit 6, Channel 0 Bit 5, Channel 0
5713 drw10
Bit 7, Channel 0
NOTE: 1. 2.048 Mb/s mode, last channel = ch 31, 4.096 Mb/s mode, last channel = ch 63, 8.192 Mb/s mode, last channel = ch 127.
Figure 7. ST-BUS(R) Timing for 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or 8.192 Mb/s, when WFPS pin = 0.
tFPW
F0i
tFPS
CLK
tFPH
tCP
tCH
tCL
tr
tf
tSOD
TX Bit 7, Last Ch(1) Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0
tSIS
RX
NOTE: 1. 2.048 Mb/s mode, last channel = ch 31, 4.096 Mb/s mode, last channel = ch 63, 8.192 Mb/s mode, last channel = ch 127.
tSIH
Bit 0, Channel 0 Bit 1, Channel 0 Bit 2, Channel 0
5713 drw11
Bit 7, Last
Ch(1)
Figure 8. GCI Timing at 2.048 Mb/s and High Speed Serial Interface at 4.096 Mb/s or 8.192 Mb/s, when WFPS pin = 0 21
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
tHFPW tHFPS
F0i
tHFPH
tHCP tHCL
HCLK 4.096 MHz
tHCH
tDIF
CLK 16.384 MHz
tHr tHf tCP
tCH
tCL
tr
tf
tSOD
TX
Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0 Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0
tSIS
RX
Bit 1, Ch 127 Bit 0, Ch 127 Bit 7, Ch 0
tSIH
Bit 6, Ch 0 Bit 5, Ch 0 Bit 4, Ch 0
5713 drw12
NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
Figure 9. WFP Bus Timing for High Speed Serial Interface (8.192 Mb/s), when WFPS pin = 1
CLK
(ST-BUS or WFPS mode)
CLK
(GCI mode)
tDZ TX
VALID DATA
tZD TX tXCD CCO
5713 drw13
ODE
VALID DATA
tODE
TX
tODE
VALID DATA
5713 drw14
Figure 10. Serial Output and External Control 22
Figure 11. Output Driver Enable (ODE)
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (INTEL)
Symbol tALW tADS tADH tALRD tDDR tCSRW tRW tCSR tDHR tWW tALWR tCSW tDSW tSWD tDHW tAKD
(1)
Parameter ALE Pulse Width Address Setup from ALE falling Address Hold from ALE falling RD Active after ALE falling Data Setup from DTA LOW on Read CS Hold after RD/WR RD Pulse Width (Fast Read) CS Setup from RD Data Hold after RD WR Pulse Width (Fast Write) WR Delay after ALE falling CS Setup from WR Data Setup from WR (Fast Write) Valid Data Delay on Write (Slow Write) Data Hold after WR Inactive Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s
Min. 20 10 10 10 10 0 0 10 45 3 0 20 5
Typ. 80
Max. 75 122 50/60 760/780 400/420 220/240
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Test Conditions
CL = 150pF
CL = 150pF, RL = 1K
CL = 150pF CL = 150pF CL = 150pF CL = 150pF CL = 150pF, RL = 1K
tAKH (1)
Acknowledgment Hold Time
45
80
NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
tALW
ALE
tADS tADH
AD0-AD7 D8-D15
ADDRESS DATA
tALRD
CS
tCSRW
tCSR
RD
tRW
tDHR
tCSW
WR
tWW tDSW
tDHW
tALWR
DTA
tSWD tAKD
tDDR
tAKH
5713 drw15
Figure 12. Multiplexed Bus Timing (Intel Mode) 23
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS - MULTIPLEXED BUS TIMING (MOTOROLA)
Symbol tASW tADS tADH tDDR tCSH tCSS tDHW tDWS tSWD tRWS tRWH tDHR(1) tDSH tAKD Parameter ALE Pulse Width Address Setup from AS falling Address Hold from AS falling Data Setup from DTA LOW on Read CS Hold after DS falling CS Setup from DS rising Data Hold after Write Data Setup from DS - Write (Fast Write) Valid Data Delay on Write (Slow Write) R/W Setup from DS Rising R/W Hold from DS Rising Data Hold after Read DS Delay after AS falling Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s 45 55/60 760/780 400/420 220/240 80 ns ns ns ns ns CL = 150pF CL = 150pF CL = 150pF CL = 150pF CL = 150pF, RL = 1K Min. 80 10 10 10 0 0 10 25 60 10 10 10 Typ. 50 Max. 122 75 Units ns ns ns ns ns ns ns ns ns ns ns ns ns CL = 150pF, RL = 1K CL = 150pF Test Conditions
tAKH(1)
Acknowledgment Hold Time
NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
DS
tRWS
R/W
tRWH
tASW
AS
tDSH
tADS
AD0-AD7 D8-D15 WR AD0-AD7 D8-D15 RD CS ADDRESS
tADH
tSW
tDHW tDWS
DATA
tDHR
ADDRESS DATA
tCSH tCSS tDDR
DTA
tAKD
tAKH
5713 drw16
Figure 13. Multiplexed Bus Timing (Motorola Mode) 24
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS-MOTOROLA NON-MULTIPLEXED BUS MODE
Symbol tCSS tRWS tADS tCSH tRWH tADH tDDR tDHR tDSW tSWD tDHW tAKD Parameter CS Setup from DS falling R/W Setup from DS falling Address Setup from DS falling CS Hold after DS rising R/W Hold after DS Rising Address Hold after DS Rising Data Setup from DTA LOW on Read Data Hold on Read Data Setup on Write (Fast Write) Valid Data Delay on Write (Slow Write) Data Hold on Write Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory @ 2.048 Mb/s @ 4.096 Mb/s @ 8.192 Mb/s 45 55/60 760/780 400/420 220/240 80 ns ns ns ns ns CL = 150pF CL = 150pF CL = 150pF CL = 150pF CL = 150pF, RL = 1K Min. 0 10 2 0 5 5 0 10 20 8 Typ. 50 Max. 75 122 Units ns ns ns ns ns ns ns ns ns ns ns CL = 150pF CL = 150pF, RL = 1K Test Conditions
tAKH(1)
Acknowledgment Hold Time
NOTE: 1. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL.
DS
tCSS
CS
tCSH
tCSS
tCSH
tRWS
R/W
tRWH
tRWS
tRWH
tADS
A0-A7 VALID WRITE ADDRESS
tADH
tADS
VALID READ ADDRESS
tADH
tSWD
AD0-AD7/ D8-D15
tDSW
tDHW tDDR
tDHR
VALID READ DATA
VALID WRITE DATA
tAKD
DTA
tAKH
tAKD
tAKH
5713 drw17
Figure 14. Motorola Non-Multiplexed Asyncronous Bus Timing
25
IDT7290820 5V TIME SLOT INTERCHANGE DIGITAL SWITCH 2,048 x 2,048
COMMERCIAL TEMPERATURE RANGE
CLK GCI CLK ST-BUS
tDSS
DS
tDSS tDSPW tCSH tCSS tCSH
tCSS
CS
tRWS
R/W
tRWH
tRWS
tRWH
tADS
A0-A7
tADH
VALID WRITE ADDRESS
tADS
tADH
VALID READ ADDRESS
tSWD
AD0-AD7 D8-D15
tDHW
VALID WRITE DATA
tDHR
VALID READ DATA
tCKAK
DTA
tDDR tAKH tCKAK tAKH
5713 drw18
Figure 15. Motorola Non-Multiplexed Syncronous Bus Timing
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ORDERING IN.ORMATION
IDT XXXXXX Device Type XX Package X Process/ Temperature Range BLANK Commercial (-40C to +85C)
J BC PQF PF
Plastic Leaded Chip Carrier (PLCC, J84-1) Ball Grid Array (BGA, BC100-1) Plastic Quad Flatpack (PQFP, PQ100-2) Thin Quad Flat Pack (TQFP, PN100-1)
7290820
2,048 x 2,048 Time Slot Interchange Digital Switch
5713 drw19
DATASHEET DOCUMENT HISTORY
5/23/2000 8/15/2000 9/22/2000 12/22/2000 01/24/2001 07/09/2001 pgs.1, 3, 18 and 25. pgs.1, 2, 3, 6, 13 and 25. pgs. 3 and 13. pgs. 7, 12, 18, 21, 22, 23, 24 and 25. pg. 1, 16 and 18. pgs. 4, 5, 12 and 25. CORPORATE HEADQUARTER 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* for Tech Support: 408-330-1753 email: FIFOhelp@idt.com
J Pkg: PQF Pkg: PF Pkg: BC Pkg: www.idt.com/docs/PSC4008.pdf www.idt.com/docs/PSC4028.pdf www.idt.com/docs/PSC4036.pdf www.idt.com/docs/PSC4084.pdf
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. IDT logo is a registered trademark of Integrated Device Technology, Inc. and the ST-BUS(R) is a trademark of Mitel Corp.
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